1. Technical Field
The present invention relates to a transmission system, a transmitter, a receiver, and a transmission method. More particularly, the present invention relates to a transmission system, a transmitter, a receiver and a transmission method for transmitting serial data by using a clock signal.
2. Related Art
A transmission system is disclosed which performs wired/wireless/optical transmission of data sequences of serial data by using a clock signal, for example, in Japanese Patent No. 3496501. Such a transmission system for serial data generally includes therein a transmitter and a receiver. The transmitter generates a data signal to be transmitted, from an original data sequence, by using the edge timing of a clock signal, and transmits the generated data signal. The receiver samples the received data signal by using the edge timing of the clock signal which is synchronized with the data signal, to read the original data sequence. Here, when there is a difference in edge timing between the clock signal and the data signal received by the receiver, the read data sequence may have bit errors.
There are mainly two different methods to enable the receiver to obtain a clock signal which is synchronized with the received data signal. According to one of the methods, the clock signal used by the transmitter to generate the data signal is transmitted to the receiver in parallel with the data signal via a transmission path different from the transmission path for the data signal. The receiver uses the received clock signal to sample the received data signal. According to the other method, the transmitter generates the data signal in which the clock signal is embedded, and transmits the generated data signal. The receiver recovers the clock signal from the received data signal, and uses the recovered clock signal to sample the data signal.
The former method has the following problem. It is assumed that successive data signals have the same value. In this case, jitter is generated by the transmission path (hereinafter referred to as “deterministic jitter”) in the data signal, but such deterministic jitter is hardly generated in the clock signal which has a regular period. Since the deterministic jitter is generated only in the data signal, the data signal and the clock signal have a difference in timing therebetween, which tends to cause bit errors.
The latter method also has a problem. The receiver has a phase locked loop (PLL) circuit which performs feedback control to cause the edge timing of the data signal received by the receiver to be synchronized with the edge timing of the clock signal recovered by the receiver. The PLL circuit includes therein a phase detector, a loop filter, and a frequency-variable oscillator.
As long as the frequency of the jitter injected to the data signal falls within the loop bandwidth of the loop filter, the phase of the clock signal is varied in accordance with the jitter injected to the data signal. If this is the case, the difference in timing between the data signal and the clock signal is reduced, and the bit errors can be thus prevented from occurring. However, when the frequency of the jitter injected to the data signal takes a value outside the loop bandwidth, the phase of the clock signal can not be varied in accordance with the jitter injected to the data signal. In this case, there is a difference in timing between the data signal and the clock signal, and bit errors may therefore occur.
The PLL circuit of the receiver performs the feedback control so that the edge timing of the recovered clock signal is synchronized with each edge timing of the data signal received by the receiver. Here, it is assumed that the successive logical values of the received data signal are the same, In this case, since no edge is present between these logical values in the data signal, the PLL circuit can not perform the feedback control.